In semiconductor design, a cell-based methodology is a method of designing integrated circuits (ICs), whereby an electronic design tool maps geometric representations of cells into a physical layout layer of the IC design. A cell can include a Boolean logic function, such as, AND, NAND, OR, NOR, XOR and inversion, a storage function, such as a flip-flop or a latch, an incomplete portion of logic, or an analog function. The cell may represent a reusable unit of logic or storage, whose design is the intellectual property (IP) of a cell designer, a manufacturer, or a third party other than the designer or manufacturer.
Design rule checking (DRC) is an area of electronic design automation that determines whether the physical layout of an IC satisfies a number of recommended parameters called design rules. Design rules, provided by designers and manufacturers, enable the cell designer to verify the correctness of a physical layout for manufacturing an IC. A design rule specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for the variability of IC manufacturing processes so as to increase yield.